International Journal of Scientific Research and Engineering Development

Deployment of fifth-generation New Radio (5G NR) networks has intensified the demand for baseband processing hardware capable of delivering multi-gigabit data rates while adhering to tight power budgets. Orthogonal Frequency Division Multiplexing (OFDM) underpins 5G NR waveform generation owing to its spectral efficiency, resistance to multipath dispersion, and affinity with massive antenna configurations. Nevertheless, mapping these algorithmic strengths onto silicon entails joint optimization of transform computation, arithmetic word length, pipeline staging, and on-chip memory allocation. This work reports a transistor-level VLSI modem architecture developed and characterized entirely within the Tanner EDA environment at the 45 nm CMOS process node. The modem integrates a 1024-point pipelined Radix-2 Decimation-in-Frequency Single-path Delay Feedback FFT/IFFT core, a Gray-coded reconfigurable QAM mapper/demapper spanning BPSK to 256-QAM, configurable cyclic prefix management circuitry, a pilot-assisted Least Squares channel estimator augmented with linear frequency-domain interpolation, and a Schmidl–Cox-based timing and carrier offset recovery block. A Karatsuba-structured complex multiplier within each butterfly stage cuts the real-multiplication count from four to three, trimming per-butterfly switching energy by approximately fifteen percent. Transient simulations confirm that the modem sustains 10 Gbps effective data rate at a 2 GHz clock, drawing 40.4 mW aggregate power and occupying an estimated 1.27 mm². The FFT core achieves output signal-to-noise ratio above 65 dB with error vector magnitude below 0.5 percent, comfortably within 3GPP limits for 256-QAM. Full transmit–receive verification across a simulated ITU Pedestrian-B propagation scenario produces zero detected errors over one million bits at 35 dB operating SNR, while channel estimation normalized mean square error settles at −28.3 dB under 20 dB pilot SNR conditions. When set beside published 28 nm FinFET and FPGA-based 5G implementations, the present 45 nm design achieves 8.7 times lower power than a throughput-equivalent FinFET ASIC, confirming the merit of the adopted pipeline and arithmetic strategies.

Nammi Jogesh, Lenka Chandini, Gunturi Thanuja, Vanavada Deepika, Chintalapudi Krupa,"An Integrated VLSI Architecture for an OFDM Modem Targeting 5G New Radio Physical Layer at 45 nm CMOS" International Journal of Scientific Research and Engineering Development, V9(2): Page(2040-2045) Mar-Apr 2026. ISSN: 2581-7175. www.ijsred.com. Published by Scientific and Academic Research Publishing.